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t
High Slew Rate, Wide Bandwidth, JFET Input Operational Amplifiers
These devices are a new generation of high speed JFET input monolithic operational amplifiers. Innovative design concepts along with JFET technology provide wide gain bandwidth product and high slew rate. Well-matched JFET input devices and advanced trim techniques ensure low input offset errors and bias currents. The all NPN output stage features large output voltage swing, no deadband crossover distortion, high capacitive drive capability, excellent phase and gain margins, low open loop output impedance, and symmetrical source/sink AC frequency response. This series of devices is available in fully compensated or decompensated (AVCL2) and is specified over a commercial temperature range. They are pin compatible with existing Industry standard operational amplifiers, and allow the designer to easily upgrade the performance of existing designs. * Wide Gain Bandwidth: 8.0 MHz for Fully Compensated Devices Wide Gain Bandwidth: 16 MHz for Decompensated Devices * High Slew Rate: 25 V/s for Fully Compensated Devices High Slew Rate: 50 V/s for Decompensated Devices * High Input Impedance: 1012
MC34080 thru MC34085
HIGH PERFORMANCE JFET INPUT OPERATIONAL AMPLIFIERS
8 1
8 1
P SUFFIX PLASTIC PACKAGE CASE 626
D SUFFIX PLASTIC PACKAGE CASE 751 (SO-8)
PIN CONNECTIONS
Offset Null Inv. Input Noninv. Input VEE
1 2 3 4 - + 8 7 6 5
NC VCC Output Offset Null
* * * * *
Input Offset Voltage: 0.5 mV Maximum (Single Amplifier) Large Output Voltage Swing: -14.7 V to +14 V for Large Output Voltage Swing: VCC/VEE = 15 V Low Open Loop Output Impedance: 30 @ 1.0 MHz Low THD Distortion: 0.01% Excellent Phase/Gain Margins: 55/7.6 dB for Fully Compensated Devices ORDERING INFORMATION
(Single, Top View) Output 1 Inputs 1 VEE
1 2 - 3+ 4 8 7 - + 6 5
VCC Output 2 Inputs 2
Op Amp Function Single Dual Quad
Fully Compensated MC34081BD MC34081BP MC34082P MC34084DW MC34084P
AVCL2 Compensated MC34080BD MC34080BP MC34083BP MC34085BDW MC34085BP
Operating Temperature Range
(Dual, Top View) Package SO-8
TA = 0 to +70C 70C
Plastic DIP Plastic DIP SO-16L
16 14 1 1
TA = 0 to +70C
Plastic DIP
P SUFFIX PLASTIC PACKAGE CASE 646
PIN CONNECTIONS
Output 1 Inputs 1
3 1 2 - + - + 16 15 14 13 + - + - 12 11 10 9
DW SUFFIX PLASTIC PACKAGE CASE 751G (SO-16L)
14
Output 4 Inputs 4 VEE Inputs 3 Output 3 NC
Output 1 Inputs 1
1 2 3 - + - +
Output 4 Inputs 4
13 12 11
1
4
1
4
VCC Inputs 2
4 5 6
VCC Inputs 2
4 5 6 + - + -
VEE Inputs 3 Output 3
10 9 8
2
3
2
3
Output 2 NC
7 8
Output 2
7
(Quad, Top View)
(c) Motorola, Inc. 1996 Rev 0
MOTOROLA ANALOG IC DEVICE DATA
1
MC34080 thru MC34085
MAXIMUM RATINGS
Rating Supply Voltage (from VCC to VEE) Input Differential Voltage Range Input Voltage Range Output Short Circuit Duration (Note 2) Operating Ambient Temperature Range Operating Junction Temperature Storage Temperature Range Symbol VS VIDR VIR tSC TA TJ Tstg Value +44 (Note 1) (Note 1) Indefinite 0 to +70 +125 - 65 to +165 Unit V V V sec C C C
NOTES: 1. Either or both input voltages must not exceed the magnitude of VCC or VEE. 2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.
Representative Schematic Diagram (Each Amplifier)
VCC 200 A 50 A 850 A Q1
D1 - Inputs + + CC CF + Q5 Q2 Q9 500 50 A 500 Q10 R6 Q11 D4 RM 100 A 300 A R3 1.0 k R4 1.0 k D3 Q3 5.0 pF 20 pF J1 J2
R1 240
Q6 18 RSC Output 700 R2 Q7
D2 CM 3.0 pF
Q8
Q4
R7 66 k VEE
1
Null Adjust (MC34080, 081)*
5
*Pins 1 & 5 (MC34080,081) should not be directly grounded or connected to VCC.
2
MOTOROLA ANALOG IC DEVICE DATA
MC34080 thru MC34085
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = - 15 V, TA = Tlow to Thigh [Note 3], unless otherwise noted.)
Characteristics Input Offset Voltage (Note 4) Single TA = +25C TA = 0 to +70C (MC34080B, MC34081B) Dual TA = +25C TA = 0 to +70C (MC34082, MC34083) Quad TA = +25C TA = 0 to +70C (MC34084, MC34085) Average Temperature Coefficient of Offset Voltage Input Bias Current (VCM = 0 Note 5) TA = +25C TA = 0 to +70C Input Offset Current (VCM = 0 Note 5) TA = +25C TA = 0 to +70C Large Signal Voltage Gain (VO = 10 V, RL = 2.0 k) TA = +25C TA = Tlow to Thigh Output Voltage Swing RL = 2.0 k, TA = +25C RL = 10 k, TA = +25C RL = 10 k, TA = Tlow to Thigh RL = 2.0 k, TA = +25C RL = 10 k, TA = +25C RL = 10 k, TA = Tlow to Thigh Output Short Circuit Current (TA = +25C) Input Overdrive = 1.0 V, Output to Ground Source Sink Input Common Mode Voltage Range TA = +25C Common Mode Rejection Ratio (RS 10 k, TA = +25C) Power Supply Rejection Ratio (RS = 100 , TA = 25C) Power Supply Current Single TA = +25C TA = Tlow to Thigh Dual TA = +25C TA = Tlow to Thigh Quad TA = +25C TA = Tlow to Thigh Symbol VIO -- -- -- -- -- -- VIO/T IIB -- -- IIO -- -- AVOL 25 15 VOH 13.2 13.4 13.4 VOL -- -- -- 13.7 13.9 -- -14.1 -14.7 -- -- -- -- -13.5 -14.1 -14.0 mA 20 20 VICR CMRR PSRR ID -- -- -- -- -- -- 2.5 -- 4.9 -- 9.7 -- 3.4 4.2 6.0 7.5 11 13 70 70 31 28 (VEE +4.0) to (VCC - 2.0) 90 86 -- -- -- -- V dB dB mA 80 -- -- -- V 0.02 -- 0.1 2.0 nA V/mV 0.06 -- 0.2 4.0 nA -- 0.5 -- 1.0 -- 6.0 -- 10 2.0 4.0 3.0 5.0 12 14 -- V/C Min Typ Max Unit mV
ISC
NOTES: (continued) 3. Tlow = 0C for MC34080B Thigh = +70C for MC34080B 0C for MC34081B +70C for MC34081B 0C for MC34084 +70C for MC34084 0C for MC34085 +70C for MC34085 4. See application information for typical changes in input offset voltage due to solderability and temperature cycling. 5. Limits at TA = +25C are guaranteed by high temperature (Thigh) testing.
MOTOROLA ANALOG IC DEVICE DATA
3
MC34080 thru MC34085
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = - 15 V, TA = +25C, unless otherwise noted.)
Characteristics Slew Rate (Vin = -10 V to +10 V, RL = 2.0 k, CL = 100 pF) Compensated AV = +1.0 AV = -1.0 Decompensated AV = +2.0 AV = -1.0 Settling Time (10 V Step, AV = -1.0) To 0.10% (1/2 LSB of 9-Bits) To 0.01% (1/2 LSB of 12-Bits) Gain Bandwidth Product (f = 200 kHz) Compensated Decompensated Power Bandwidth (RL = 2.0 k, VO = 20 Vpp, THD = 5.0%) Compensated AV = +1.0 Decompensated AV = - 1.0 Phase Margin (Compensated) RL = 2.0 k RL = 2.0 k, CL = 100 pF Gain Margin (Compensated) RL = 2.0 k RL = 2.0 k, CL = 100 pF Equivalent Input Noise Voltage RS = 100 , f = 1.0 kHz Equivalent Input Noise Current (f = 1.0 kHz) Input Capacitance Input Resistance Total Harmonic Distortion AV = +10, RL = 2.0 k, 2.0 VO 20 Vpp, f = 10 kHz Channel Separation (f = 10 kHz) Open Loop Output Impedance (f = 1.0 MHz) Symbol SR 20 -- 35 -- ts -- -- GBW 6.0 12 BWp -- -- m -- -- Am -- -- en In Ci ri THD -- Zo -- -- -- -- -- -- -- 7.6 4.5 30 0.01 5.0 1012 0.05 120 35 -- -- -- -- -- -- -- -- -- nV/ Hz pA/ Hz pF % dB 55 39 -- -- 400 800 -- -- Degrees dB 8.0 16 -- -- kHz 0.72 1.6 -- -- MHz 25 30 50 50 -- -- -- -- s Min Typ Max Unit V/s
VICR , INPUT COMMON MODE VOLTAGE RANGE (V)
Figure 1. Input Common Mode Voltage Range versus Temperature
0 VCC/VEE = 3.0 V to 22 V VIO = 5.0 mA 100 k VCC IIB , INPUT BIAS CURRENT (pA) 10 k 1.0 k 100 10 1.0 -55
Figure 2. Input Bias Current versus Temperature
VCC/VEE = 15 V VCM = 0 V
-1.0 3.0 2.0 1.0 VEE 0 -55 -25 0 25 50 75 100 125
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
4
MOTOROLA ANALOG IC DEVICE DATA
MC34080 thru MC34085
Figure 3. Input Bias Current versus Input Common Mode Voltage
140 I IB , INPUT BIAS CURRENT (pA) 120 100 80 60 40 20 -12 VO, OUTPUT VOLTAGE SWING (Vpp ) VCC/VEE = 15 V TA = 25C 50 40 RL Connected to Ground TA = 25C
Figure 4. Output Voltage Swing versus Supply Voltage
30 RL = 10 k 20 10 0
RL = 2.0 k
-8.0 -4.0 0 4.0 8.0 VIC, INPUT COMMON MODE VOLTAGE (V)
12
0
5.0
10 15 20 VCC |VEE|, SUPPLY VOLTAGE (V)
25
Figure 5. Output Saturation versus Load Current
V sat , OUTPUT SATURATION VOLTAGE (V) V sat , OUTPUT SATURATION VOLTAGE (V) 0 VCC -1.0 -2.0 -3.0 1.0 0 Sink VEE 0 4.0 8.0 IL, LOAD CURRENT (mA) 12 16 VCC/VEE = +15 V to +22 V TA = 25C Source 0
Figure 6. Output Saturation vesus Load Resistance to Ground
VCC -2.0 -4.0 2.0 1.0 VEE 0 300 3.0 k 30 k 300 k VCC/VEE = 15 V TA = 25C
RL, LOAD RESISTANCE TO GROUND ()
Figure 7. Output Saturation versus Load Resistance to VCC
I SC , OUTPUT SHORT CIRCUIT CURRENT (mA) V sat , OUTPUT SATURATION VOLTAGE (V) 0 VCC 40
Figure 8. Output Short Circuit Current versus Temperature
-0.4
30 Sink 20
Source
-0.8 2.0 1.0 VEE 0 300 3.0 k 30 k 300 k VCC/VEE = +15 V RL to VCC TA = 25C
10
VCC/VEE = 15 V RL 0.1 Vin = 1.0 V -25 0 25 50 75 100 125
0 -55
RL, LOAD RESISTANCE TO VCC ()
TA, AMBIENT TEMPERATURE (C)
MOTOROLA ANALOG IC DEVICE DATA
5
MC34080 thru MC34085
Figure 9. Output Impedance versus Frequency
80 Z O , OUTPUT IMPEDANCE ( ) Z O , OUTPUT IMPEDANCE ( ) VCC/VEE = 15 V VCM = 0 VO = 0 IO = 0.5 mA TA = 25C Compensated Units Only 80 VCC/VEE = 15 V VCM = 0 VO = 0 IO = 0.5 mA TA = 25C Decompensated Units Only
Figure 10. Output Impedance versus Frequency
60
60
40
40
20 AV = 1000 0 1.0 k 10 k AV = 100 100 k f, FREQUENCY (Hz)
AV = 1.0 AV = 10 1.0 M 10 M
20 AV = 1000 0 1.0 k 10 k AV = 100 100 k f, FREQUENCY (Hz) AV = 10 1.0 M AV = 2.0 10 M
Figure 11. Output Voltage Swing versus Frequency
28 VO, OUTPUT VOLTAGE SWING (Vpp ) THD, OUTPUT DISTORTION (%) 24 20 16 12 8.0 4.0 0 10 k 100 k 1.0 M 10 M Compensated Units AV = +1.0 VCC/VEE = 15 V RL = 2.0 k THD = 1.0% TA = 25C Decompensated Units AV = -1.0 0.5
Figure 12. Output Distortion versus Frequency
AV = 1000 0.4 0.3 0.2 AV = 100 0.1 0 10 100 AV = 10 AV = 1.0* 1.0 k f, FREQUENCY (Hz) 10 k 100 k VCC/VEE = 15 V VO = 2.0 Vpp RL = 2.0 k TA = 25C *Compensated Units Only
f, FREQUENCY (Hz)
Figure 13. Open Loop Voltage Gain versus Temperature
A VOL , OPEN LOOP VOLTAGE GAIN (dB NORMALIZED) 1.08 1.04 1.00 0.96 0.92 -55 -25 0 25 50 75 100 125 VCC/VEE = 15 V VO = -10 V to +10 V RL = 10 k f 10 Hz
TA, AMBIENT TEMPERATURE (C)
6
MOTOROLA ANALOG IC DEVICE DATA
MC34080 thru MC34085
Figure 14. Open Loop Voltage Gain and Phase versus Frequency
A VOL, OPEN LOOP VOLTAGE GAIN (dB) VCC/VEE = 15 V VO = 0 V RL = 2.0 k TA = 25C Phase Gain 90 40 135 20 Solid Line Curves -- Compensated Units Dashed Line Curves -- Decompensated Units 0 1.0 10 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) 1.0 M 10 M 180 100 M A VOL, OPEN LOOP VOLTAGE GAIN (dB) 100 80 60 20 10 0 VCC/VEE = 15 V VO = 0 V Phase TA = 25C Margin -10 = 54 -20 1 -- Gain, RL = 2.0 k 2 -- Gain, RL = 2.0 k, CL = 100 pF -30 3 -- Phase, RL = 2.0 k 4 -- Phase, RL = 2.0 k, CL = 100 pF Compensated Units Only 4 -40 1.0 2.0 3.0 5.0 7.0 10 f, FREQUENCY (Hz) Gain Margin = 7.6 dB 1 2 3 20 30 120 140 160 180 200 50 , EXCESS PHASE (DEGREES) 100 0 45
Figure 15. Open Loop Voltage Gain and Phase versus Frequency
GBW, GAIN BANDWIDTH PRODUCT (NORMALIZED)
Figure 16. Open Loop Voltage Gain and Phase versus Frequency
A VOL, OPEN LOOP VOLTAGE GAIN (dB) 20 100 10 VCC/VEE = 15 V 0 VO = 0 V TA = 25C Phase Margin -10 = 43 -20 1 -- Gain, RL = 2.0 k 2 -- Gain, RL = 2.0 k, CL = 100 pF -30 3 -- Phase, RL = 2.0 k 4 -- Phase, RL = 2.0 k, CL = 100 pF Decompensated Units Only -40 1.0 2.0 3.0 5.0 7.0 10 f, FREQUENCY (Hz) Gain Margin = 5.5 dB , EXCESS PHASE (DEGREES) 120 140 160 180 200 20 30 50
, EXCESS PHASE (DEGREES)
Figure 17. Normalized Gain Bandwidth Product versus Temperature
1.20 VCC/VEE = 15 V RL = 2.0 k
1.10
1.00
0.90
0.80 -55
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
Figure 18. Percent Overshoot versus Load Capacitance
100 M , PHASE MARGIN (DEGREES) 80 60 40 Compensated Units AV = +1.0 VCC/VEE = 15 V RL = 2.0 k VO = 100 mVpp VO = -10 V to +10 V TA = 25C 100 CL, LOAD CAPACITANCE (pF) 1.0k Decompensated Units AV = +2.0 70 60 50 40 30 20 10 0 10
Figure 19. Phase Margin versus Load Capacitance
Compensated Units AV = +1.0 VCC/VEE = 15 V RL = 2.0 k to VO = 100 mVpp VO = -10 V to +10 V TA = 25C
PERCENT OVERSHOOT
R
20 0 10
Decompensated Units AV = +2.0 100 CL, LOAD CAPACITANCE (pF) 1.0k
MOTOROLA ANALOG IC DEVICE DATA
7
MC34080 thru MC34085
Figure 20. Gain Margin versus Load Capacitance
10 8.0 6.0 4.0 2.0 0 10 Decompensated Units AV = +2.0 Compensated Units AV = +1.0 m , PHASE MARGIN (DEGREES) VCC/VEE = 15 V RL = 2.0 k to VO = 100 mVpp VO = -10 V to +10 V TA = 25C 60 50 40 30 20 CL = 360 pF 10 0 -55 VO = 100 mVpp VCC/VEE = 15 V VO = -10 V to +10 V CL = 200 pF RL = 2.0 k to -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) CL = 100 pF Solid Line Curves-Compensated Units AV = +1.0 CL = 10 pF Dashed Line Curves-Decompensated Units AV = +2.0
Figure 21. Phase Margin versus Temperature
A m, GAIN MARGIN (dB)
100 CL, LOAD CAPACITANCE (pF)
10 k
Figure 22. Gain Margin versus Temperature
10 8.0 6.0 4.0 2.0 0 -55 CL = 100 pF CL = 200 pF CL = 360 pF -25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (C) SR, SLEW RATE (NORMALIZED) Solid Line Curves-Compensated Units AV = +1.0 Dashed Line Curves-Decompensated Units AV = +2.0 1.40
Figure 23. Normalized Slew Rate versus Temperature
VCC/VEE = 15 V AV = +1.0 for Compensated Units AV = -1.0 for Decompensated Units RL = 2.0 k CL = 100 pF VO = -10 V to +10 V
A m, GAIN MARGIN (dB)
1.20
CL = 10 pF
VCC/VEE = 15 V RL = 2.0 k to
VO = 100 mVpp VO = -10 V to +10 V
1.00
0.80
0.60 -55
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
8
MOTOROLA ANALOG IC DEVICE DATA
MC34080 thru MC34085
MC34084 Transient Response AV = +1.0, RL = 2.0 k, VCC/VEE = 15 V, TA = 25C Figure 24. Small Signal
CL = 10 pF
Figure 25. Large Signal
CL = 100 pF
0
0
0.2 s/Div
0.5 s/Div
MC34085 Transient Response AV = +2.0, RL = 2.0 k, VCC/VEE = 15 V, TA = 25C Figure 26. Small Signal
CL = 10 pF
Figure 27. Large Signal
CL = 100 pF
0
0
0.2 s/Div
0.5 s/Div
MOTOROLA ANALOG IC DEVICE DATA
5.0 mV/Div
50 mV/Div
5.0 mV/Div
50 mV/Div
9
MC34080 thru MC34085
Figure 28. Common Mode Rejection Ratio versus Frequency
100 TA = 25C 80 60 40 20 0 0.1
VCC VCC + - VEE VEE VO
CMRR, COMMON MODE REJECTION RATIO (dB)
PSSR, POWER SUPPLY REJECTION RATIO (dB)
Figure 29. Power Supply Rejection Ratio versus Frequency
120 100 80 60 40 20
VEE VEE VCC VCC + - VO
TA = -55C
TA = 125C
VCC/VEE = 15 V VS = 3.0 V VO = 0 V
VCC/VEE = 15 V VS = 3.0 V VO = 0 V TA = 25C Positive Supply
Compensated Units AV = +1.0 Decompensated Units AV = +2.0 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M 10 M
Negative Supply 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 1.0 M 10 M
1.0
10
0 0.1
1.0
10
PSSR, POWER SUPPLY REJECTION RATION (dB)
Figure 30. Power Supply Rejection Ratio versus Temperature
110 I CC , SUPPLY CURRENT (NORMALIZED) 1.20
Figure 31. Normalized Supply Current versus Supply Voltage
TA = 125C 1.10 1.00 0.90 0.80 0.70 TA = 25C Supply Current Normalized to VCC/VEE = 15 V, TA = 25C RL = VO = 0 0 5.0 10 15 TA = -55C 20 25
100
Negative Supply
90
VCC VCC + - VEE VEE
VCC/VEE = 15 V VS = 3.0 V VO = 0 V f 10 Hz
80
VO
Positive Supply Compensated Units AV = +1.0 Decompensated Units AV = +2.0
70 -55
-25
0
25
50
75
100
125
TA, AMBIENT TEMPERATURE (C)
VS, SUPPLY VOLTAGE (V)
Figure 32. Channel Separation versus Frequency
120 CHANNEL SEPERATION (dB) 100 80 60 40 20 VCC/VEE = 15 V TA = 25C e n , INPUT NOISE VOLTAGE (nV/ Hz ) 100 80 60 40 20 0 10
Figure 33. Spectral Noise Density
VCC/VEE = 15 V VCM = 0 TA = 25C
0 10 k
100 k 1.0 M f, FREQUENCY (Hz)
10 M
100
1.0 k f, FREQUENCY (Hz)
10 k
100 k
10
MOTOROLA ANALOG IC DEVICE DATA
MC34080 thru MC34085
APPLICATIONS INFORMATION
The bandwidth and slew rate of the MC34080 series is nearly double that of currently available general purpose JFET op-amps. This improvement in AC performance is due to the P-channel JFET differential input stage driving a compensated miller integration amplifier in conjunction with an all NPN output stage. The all NPN output stage offers unique advantages over the more conventional NPN/PNP transistor Class AB output stage. With a 10 k load resistance, the op amp can typically swing within 1.0 V of the positive rail (VCC), and within 0.3 V of the negative rail (VEE), providing a 28.7 p-p swing from 15 V supplies. This large output swing becomes most noticeable at lower supply voltages. If the load resistance is referenced to VCC instead of ground, the maximum possible output swing can be achieved for a given supply voltage. For light load currents, the load resistance will pull the output to VCC during the positive swing and the NPN output transistor will pull the output very near VEE during the negative swing. The load resistance value should be much less than that of the feedback resistance to maximize pull-up capability. The all NPN transistor output stage is also inherently fast, contributing to the operation amplifier 's high gain-bandwidth product and fast settling time. The associated high frequency output impedance is 50 (typical) at 8.0 MHz. This allows driving capacitive loads from 0 pF to 300 pF without oscillations over the military temperature range, and over the full range of output swing. The 55C phase margin and 7.6 dB gain margin as well as the general gain and phase characteristics are virtually independent of the sink/source output swing conditions. The high frequency characteristics of the MC34080 series is especially useful for active filter applications. The common mode input range is from 2.0 V below the positive rail (VCC) to 4.0 V above the negative rail (VEE). The amplifier remains active if the inputs are biased at the positive rail. This may be useful for some applications in that single supply operation is possible with a single negative supply. However, a degradation of offset voltage and voltage gain may result. Phase reversal does not occur if either the inverting or noninverting input (or both) exceeds the positive common mode limit. If either input (or both) exceeds the negative common mode limit, the output will be in the high state. The input stage also allows a differential up to 44 V, provided the maximum input voltage range is not exceeded. The supply voltage operating range is from 5.0 V to 22 V. For optimum frequency performance and stability, careful component placement and printed circuit board layout should be exercised. For example, long unshielded input or output leads may result in unwanted input-output coupling. In order to reduce the input capacitance, resistors connected to the input pins should be physically close to these pins. This not only minimizes the input pole for optimum frequency response, but also minimizes extraneous "pickup" at this node. Supply decoupling with adequate capacitance close to the supply pin is also important, particularly over temperature, since many types of decoupling capacitors exhibit large impedance changes over temperature. Primarily due to the JFET inputs of the op amp, the input offset voltage may change due to temperature cycling and board soldering. After 20 temperature cycles (- 55 to 165C), the typical standard deviation for input offset voltage is 559 V in the plastic packages. With respect to board soldering (260C, 10 seconds), the typical standard deviation for input offset voltage is 525 V in the plastic package. Socketed devices should be used over a minimal temperature range for optimum input offset voltage performance.
Figure 34. Offset Nulling Circuit
VCC 3+ 2 4 - 7 6 5 1 5.0 k
VEE
MOTOROLA ANALOG IC DEVICE DATA
11
MC34080 thru MC34085
OUTLINE DIMENSIONS
P SUFFIX PLASTIC PACKAGE CASE 626-05 ISSUE K
8 5
-B-
1 4
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
F
NOTE 2
-A- L
C -T-
SEATING PLANE
J N D K
M
M
H
G 0.13 (0.005) TA
M
B
M
D SUFFIX PLASTIC PACKAGE CASE 751-05 (SO-8) ISSUE R A
8
D
5
C
E
1 4
H
0.25
M
B
M
h B C e A
SEATING PLANE
X 45 _
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.18 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_
q
L 0.10 A1 0.25 B
M
CB
S
A
S
q
12
MOTOROLA ANALOG IC DEVICE DATA
MC34080 thru MC34085
OUTLINE DIMENSIONS
P SUFFIX PLASTIC PACKAGE CASE 646-06 ISSUE L
NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01
14
8
B
1 7
A F C N H G D
SEATING PLANE
L
J K M
DW SUFFIX PLASTIC PACKAGE CASE 751G-02 (SO-16L) ISSUE A -A-
16 9
-B-
1 8
8X
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
16X
D
M
J TA
S
0.010 (0.25)
B
S
F R X 45_ C -T-
14X
G
K
SEATING PLANE
M
DIM A B C D F G J K M P R
MOTOROLA ANALOG IC DEVICE DATA
13
MC34080 thru MC34085
NOTES
14
MOTOROLA ANALOG IC DEVICE DATA
MC34080 thru MC34085
NOTES
MOTOROLA ANALOG IC DEVICE DATA
15
MC34080 thru MC34085
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16
MOTOROLA ANALOG IC DEVICE DATA
*MC34080/D*
MC34080/D

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